If there is noise on so on affecting the SDA line, a discrepancy may be generated between the master and slave clocks.
Whether noise, etc. on the SCL line is recognized as a clock pulse depends on the differences between the device Vih/Vil characteristics and noise filtering capabilities of both sides. When it is recognized as a clock pulse, this generates a discrepancy between the clocks of the two sides. This discrepancy may cause the level of the SDA line to be fixed low. Mainly, during master transmit operation, an ACK output from the slave fixes the SDA level to low, and during master receive operation, data transmission from the slave stops mid-transmission (0 output). To clear the condition when the level of the SDA line is fixed low on the slave side, first switch the SCL/SDA pins on the master side to general ports, output a dummy clock (Hi-z and low pulse) from pins shared with SCL, and confirm release of SDA on the slave side. If the first dummy clock output doesn't release the SDA on the slave side, repeat otuputting until it does. After SDA is released on the slave side, return the settings on the master side to IIC bus, issue the start and stop conditions, and end transmission. The IIC bus of most slave devices will be reset by either the start or stop condition in this case, so you will need to perform the settings again in order to retransmit. The reset method is explained in the manual for some slave devices, so please follow the directions for your device if it is included in the manual. For the clearing condition when SDA is fixed to low level on the master side, refer to FAQ No.107070 or FAQ No.107073. The clearing condition differs by product.
|H8S/2630, 2639, 2638, 2636, 2635|
|H8S/2556, 2552, 2506|
|H8S/2472, 2463, 2462|
|H8S/2258, 2239, 2238, 2237, 2227|