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ISEL to 11b using DMAC; subsequent interrupts don't make DMAC transfer

Latest Updated:08/30/2011

Question:

I set the interrupt destination bit (ISEL) in the interrupt request destination setting register (ISELR) to 11b using the DMAC, but the second and subsequent interrupts do not perform DMAC transfer.

Answer:

If the ISEL bits in the ISELR register are set to 11b by DMAC transfer, it is automatically updated to 00b after the DMAC is activated.
At this time, the interrupt status flag (IR) in the interrupt request register (IR) is not cleared and an interrupt request is output to the CPU.
Although it is possible to both activate the DMAC and send an interrupt request to the CPU with a single request using this method, because the ISEL bits are automatically updated to 00b, in order to send a second request to both the DMAC and the CPU, the ISEL bits must first be set to 11b again.

For details, please refer to Selecting Interrupt Request Destinations in the Operation section of the Interrupt Control Unit (ICU) chapter of the hardware manual.

Suitable Products
RX610