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Does write back process done by prioritizing CPU access and DMA access?

Latest Updated:03/24/2009

Question:

When it is the operand cache write back mode and the write back is executed by memory allocation cache access, is the write back process executed by giving priority more than CPU access and the DMA access?

Answer:

During the write back processing of 16 bytes, the I-BUS access of other CPU and DMAC is never generated.
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SH7206
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