First of all, please confirm the following points.
1) Is each power supply supplied correctly?
2) Is the power voltage stable?
3) Is there any problem in clock peripheral circuit?
･Please decide it after consulting enough with the oscillator maker so that the circuit constant of oscillation circuit is different depending on the stray capacity of the oscillator and mounting circuit.
4) Does not the internal clock exceed a regulated range?
The low multiplication of internal PLL circuit is decided by setting the clock mode. The internal clock such as peripheral clock, and system clock must not exceed a regulated range by this setting.
5) The reset sequence is followed?
6) Is the expected frequency output from the CK pins (system clock output pins)?
7) Is the program correctly written in on-chip ROM?
8) Are the unused pins correctly processed?
•Connect nothing to the NC pin.
•Fix the unused input pins to the high or low level.
9) Is the wait pin negated?
10) Is undefined and reserve address being accessed?
11) Even if devices are changed, is the same phenomenon generated?
|SH7052, SH7053, SH7054|
|SH7047, SH7049, SH7105, SH7107, SH7109|
|SH7046, SH7148, SH7101, SH7048, SH7104, SH7106, SH7108|
|SH7040, SH7041, SH7042, SH7043, SH7044, SH7045|
|SH7032, SH7034, SH7034B|
|SH7014, SH7016, SH7017|