What will happen if the TFRST bit and RFRST bit in the FIFO control register (SCFCR) of the serial communication interface with FIFO (SCIF) is set to 1 during the transmit operation? Is the transmission aborted at the same time whe bits TFRST and RFRST are set to 1?
When TFRST is 1, the transmit FIFO data register (SCFTDR) is reset, however, the transmit shift register (SCTSR) continues the operation. Therefore the transmit data that has already been transferred to the SCTSR will be transmitted. When RFRST is 1, the receive FIFO data register (SCFERDR) is reset, but the receive shift register (SCRSR) continues the operation. Therefore the receive data that has been completely received after RFRST=1 will be transferred from SCRSR to SCFRDR sequentially. Note that the SCFRDR reset is hold while RFRST=1. In this state, correct data cannot be read even reading the SCFRDR.
|SH7083, SH7084, SH7085, SH7086|